Microchip Technology dsPIC33CK 16-Bit Digital Signal Controllers

Microchip Technology dsPIC33CK 16-Bit Digital Signal Controllers (DSCs) are designed to integrate control attributes of MCUs with the computation capabilities of DSPs in a single core. These dsPIC33CK DSCs feature a 16-bit CPU, high-resolution PWM, CAN Flexible Data (CAN FD), internal oscillator, low-power management modes, high-speed ADC module, and debugger development support. The 16-bit CPU has a modified Harvard architecture with an enhanced instruction set and support for Digital Signal Processing (DSP). The dsPIC33CK DSCs have internal flash program memory that is readable, writable, and erasable during normal operation over the entire V_DD range. The flash program memory stores and executes application codes.

The dsPIC33CK DSCs have an on-chip Phase-Locked Loop (PLL) to boost internal operating frequency on select internal/external oscillator sources. The Auxilliary PLL (APLL) clock generator boosts operating frequency for peripherals, and the Fail-Safe Clock Monitoring (FSCM) detects clock failure and permits safe application recovery/shutdown. The dsPIC33CK DSCs implement two instances of the Quadrature Encoder Interface (QEI) module that provides the interface to incremental encoders for obtaining mechanical position data. The QEI module enables closed-loop control of motor control appliances, including AC Induction Motors (ACIM) and Switched Reluctance (SR).

Features

16-bit dsPIC33CK CPU
Clock management
- Internal oscillator
- Programmable PLLs and oscillator clock sources
- Reference clock output
- Fail-Safe Clock Monitor (FSCM)
- Backup internal oscillator
Low-power management modes
High-speed PWM
- 8 PWM pairs
- Dead time for rising and falling edges
- Dead-time compensation
- Clock chopping for high-frequency operation
- Flexible trigger configuration for ADC triggering
One general-purpose timers
High-speed ADC module
Up to 24 input channels
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Four digital comparators
- Four oversampling filters for increased resolution
- Up to three Op Amps

Four Direct Memory Access (DMA) channels
Communication interfaces
- Three 4-wire SPI/I²S modules
- CAN Flexible Data (FD) module
- Three I²C modules with SMBus support
- Programmable Cyclic Redundancy Check (CRC)
- Parallel Master Port (PMP)
Debugger development support
- In-circuit and in-application programming and debugging
- Three complexes and five simple breakpoints
- The trace buffer and run-time watch
Clock monitor system with backup oscillator
Deadman Timer (DMT)
Error Correcting Code (ECC)
Watchdog Timer (WDT)
CodeGuard™ security
ICSP™ write inhibit
RAM Memory Built-In Self-Test (MBIST)