In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.
The received signals are digitized with four high dynamic range, continuous time, Digma-Delta (Σ-Δ) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out-of-band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional Intermediate Frequency (IF) receivers.
The fully integrated Phase-Locked Loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF Local Oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All Voltage Controlled Oscillators (VCOs) and loop filter components are integrated.
The high speed JESD204B interface supports up to 12.288Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.
The core of the ADRV9008-1 can be powered directly from 1.3V and 1.8V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12mm × 12mm, 196-ball chip scale ball grid array (CSP_BGA).