Microchip Technology IGLOO Low Power Flash FPGAs

Microchip IGLOO Low Power Flash FPGAs offer a single-chip solution, re-programmability, advanced features, and small footprint packages. These FPGAs incorporate Flash*Freeze technology that enables entering and exiting an ultra-low power mode by consuming as low as 5μW power while retaining SRAM and registering data. This technology also simplifies power management through I/O and clock management with rapid recovery to an operation mode. The IGLOO devices also incorporate non-volatile flash technology that instantly brings the secure, low-power, and single-chip solution. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. The IGLOO FPGAs offer 1kb of on-chip, reprogrammable, non-volatile FlashROM storage and clock conditioning circuitry based on an integrated Phase-Locked Loop (PLL). These devices support the ARM-Cortex-M1 soft processor that offers the benefits of programmability and time-to-market. These Flash FPGAs are ideally used in consumer, industrial, communications, computing, networking, and avionics applications.

Features

Low power:
- 1.2V to 1.5V core voltage support for low power
- Supports single-voltage system operation
- 5μW power consumption in Flash*Freeze mode
- Low-power active FPGA operation
- Flash*Freeze technology enables ultra-low power
- Consumption while maintaining FPGA content
- Easy entry to / exit from ultra-low power Flash*Freeze mode
High capacity:
- 15K to 1M system gates
- Up to 144Kb of true dual-port SRAM
- Up to 300 users I/Os
Reprogrammable flash technology:
- 130nm, 7-layer metal, flash-based CMOS process
- Instant on level 0 support
- Single-chip solution
- Retains programmed design when powered off
- 250MHz for 1.5V systems and 160MHz for 1.2V systems
High-performance routing hierarchy:
- Segmented, hierarchical routing, and clock structure
In-System Programming (ISP) and security:
- ISP using on-chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM^®-enabled IGLOO^® devices) via JTAG (IEEE
- 1532–compliant)
- FlashLock^® to secure FPGA contents
Embedded Memory:
- 1Kb of FlashROM user non-volatile memory
- SRAMs and FIFOs with variable-aspect-ratio 4608-Bit RAM blocks (×1, ×2, ×4, ×9, and ×18 organizations)
- True dual-port SRAM (except ×18 organization)

Advanced I/O:
- 700Mbps DDR, LVDS-capable I/Os (AGL250 and above)
- 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V mixed-voltage operation
- Wide range power supply voltage support per JESD8-B, allowing I/Os to operate from 2.7V to 3.6V
- Wide range power supply voltage support per JESD8-12, allowing I/Os to operate from 1.14V to 1.575V
- Bank-selectable I/O voltages up to 4 banks per chip
- Single-ended I/O standards: LVTTL, LVCMOS 3.3V/2.5V/1.8V/1.5V/1.2V, 3.3V PCI/3.3V PCI-X, and LVCMOS 2.5V/5V input
- Differential I/O standards: LVPECL, LVDS, B-LVDS, and M-LVDS (AGL250 and above)
- I/O registers on input, output, and enable paths
- Hot-swappable and cold-sparing I/Os
- Programmable output slew rate and drive strength
- Weak pull-up/pull-down
- IEEE 1149.1 (JTAG) Boundary-Scan test
- Pin-compatible packages across the IGLOO family
Clock Conditioning Circuit (CCC) and PLL:
- Six CCC blocks and one with an integrated PLL
- Configurable phase-shift, multiply/divide, delay capabilities, and external feedback
- 1.5MHz to 250MHz wide input frequency range
ARM processor support in IGLOO FPGAs:
- M1 IGLOO devices - Cortex^®-M1 soft processor available with or without debug